The Xilinx ISE design tool is used for FPGA implementation. The simulation is performed using ModelSim. The RTL design of proposed new Braun Multiplier and standard braun multiplier is done using Verilog HDL. This research also presents a comparative study of FPGA implementation on Spartan2 and Spartartan2E for new multiplier design and standard braun multiplier. The architecture of standard Braun Multiplier is modified in this work for reducing the delay due to Ripple Carry Adder and performing faster multiplication of two binary numbers. In this research work, a new design of Braun Multiplier is proposed and this proposed design of multiplier uses a very fast parallel prefix adder ( Kogge Stone Adder) in place of Ripple Carry Adder. The architecture of Braun multiplier mainly consists of some Carry Save Adders, array of AND gates and one Ripple Carry Adder. Braun multiplier is a type of parallel array multiplier. A typical implementation of such an array multiplier is Braun design. This requires a parallel array multiplier to achieve high execution speed or to meet the performance demands. Over the years the computational complexities of algorithms used in Digital Signal Processors (DSPs) have gradually increased. Multiplication is the basic building block for several DSP processors, Image processing and many other. ISSN 2229-5518 Design of Braun Multiplier with Kogge Stone Adder & It’s Implementation on FPGA Ms. International Journal of Scientific & Engineering Research, Volume 3, Issue 10, October-2012 1 Design of Braun Multiplier with Kogge Stone Adder & It’s Implementation on FPGA
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